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(jc64 package) product manual preliminary version 1.1 document no. 80-36-00592 february 2007 sandisk corporation corporate headquarters ? 601 mccarthy boulevard ? milpitas, ca 95035 phone (408 ) 801-1000 ? fax (408) 801-8657 www.sandisk.com
revision 1.1 preliminary sandisk inand product manual ? 2007 sandisk corporation i sandisk ? corporation general policy does not recommend the use of its products in life support applic ations where in a failure or malfunction of the product may directly threaten life or in jury. per sandisk terms and conditions of sale, the user of sandi sk products in life support applicati ons assumes all risk of such use and indemni fies sandisk against all damages. see ?disclaimer of liability.? this document is for information use only and is subject to change without prior notice . sandisk corporation assumes no responsibility for any errors that may appear in this document, nor for incidental or consequential damages resulting from the furnishing, performance or use of this ma terial. no part of this document may be reproduced, transmitted, transcribed, stored in a retrievable manner or translated into any language or computer language, in an y form or by any means, electronic, mechanical, magnetic, optical, chemical, manual or otherwise, without the prior written consent of an officer of sandisk corporation. all parts of the sandisk documentation are protecte d by copyright law and all rights are reserved. sandisk and the sandisk logo are registered trademarks of sandis k corporation. product names mentioned herein are for identification purposes only and may be trademarks and/or registered trade marks of their respective companies. ? 2007 sandisk corporation. all rights reserved. sandisk products are covered or licensed under one or more of the following u.s. pate nt nos. 5,070,032; 5,095,344; 5,168,465; 5,172,338; 5,198,380; 5,200,959; 5,268,318; 5,268,870; 5,272,669; 5,418,752; 5,602,987 . other u.s. and foreign patents awarded and pending. lit. no. 80-36-00592 rev. 1.1 (d2) 02/07 printed in u.s.a. revision history january 2007 revision 1.0?prelimi nary draft of initial release february 2007 revision 1.1?added toc; removed section 2.6; corrected fig. 2-2; revise d capacitor specifications and part numbers; eliminated warranty section.
revision 1.1 preliminary sandisk inand product manual ? 2007 sandisk corporation ii table of contents 1. introduction...................................................................................................1-1 1.1 general description ................................................................................1-1 1.2 features...................................................................................................1-2 1.3 document scope.....................................................................................1-2 1.4 inand standard ....................................................................................1-2 1.5 functional de scription............................................................................1-3 1.6 technology independence ......................................................................1-3 1.7 defect and error management................................................................1-3 1.8 wear leveling.........................................................................................1-3 1.9 automatic sleep mode ...........................................................................1-3 1.10 inand?sd bus mode ........................................................................1-4 1.11 spi mode ...............................................................................................1-5 2. product specifications...................................................................................2-1 2.1 overview ................................................................................................2-1 2.2 typical card po wer requirements .........................................................2-1 2.3 operating conditions..............................................................................2-1 2.4 system performance ...............................................................................2-2 2.5 system reliability and maintenance ......................................................2-2 2.6 physical sp ecificatio ns ...........................................................................2-3 3. inand interface description .......................................................................3-1 3.1 pins and registers...................................................................................3-1 3.2 bus topologies .......................................................................................3-3 3.3 electrical interface..................................................................................3-3 3.4 inand registers....................................................................................3-3 3.5 data interchange form at and card sizes ...............................................3-8 4. inand protocol description ........................................................................4-1 4.1 general ...................................................................................................4-1 4.2 sd bus protocol .....................................................................................4-1 4.3 functional de scription............................................................................4-1 appendix a power delivery and capacitor specifications .........................a-1 appendix b ordering information .............................................................. b-1 appendix c disclaim er of liability ............................................................ c-1
chapter 1 ? introduction revision 1.1 preliminary sandisk inand product manual ? 2007 sandisk corporation 1-1 02/09/07 1 introduction 1.1 general description the sandisk inand is a very small, flash stor age device, designed specifically for storage applications that put a premium on small form factor, low power and lo w cost. flash is the ideal storage medium for portable, battery-powered devices. it features low power consumption and is non-volatile, requiring no power to maintain the stored data. it also has a wide operating range for temperature, shock and vibration. it is compatible with the jc64 fbga 169, 0.5mm ball pitch, package. sandisk inand is well-suited to meet the n eeds of small, low power, electronic devices. with form factors measuring 12mm x 16mm x 1.2 mm and 12mm x 18mm x 1.2mm, inand is expected to be used in a wide variety of portable devices like mobile phones, pagers, and voice recorders. to support this wide range of applications, in and is offered with an sd interface. the sd interface product is fully compatible with inand products, and provides a 4-bit data bus for maximum performance. for compatibility w ith existing controllers, the inand offers, in addition to these interfaces, an alternate communication-protocol based on the spi standard. these interfaces allow for easy integration into any design, regardless of which type of microprocessor is used. all device and inte rface configuration data (such as maximum frequency and card identification) are stored on the device. the sandisk inand provides up to 8 gb of memory for use in mass storage applications. in addition to the mass-storage-specific flash memory chip, inand includes an intelligent controller, which manages interface protocols, data storage and retrie val, error correction code (ecc) algorithms, defect handling and diagnostics, power management, wear leveling, and clock control. figure 1-1 is a block diagram of the sandisk inand with sd interface. figure 1-1 sandisk inand block diagram sd bus/spi bus interface flash memory sandisk single chip controller control data in/out sandisk inand2
chapter 1 ? introduction revision 1.1 preliminary sandisk inand product manual ? 2007 sandisk corporation 1-2 02/09/07 1.2 features sandisk inand product features include the following. ? up to 8 gb of data storage ? sd-protocol compatible ? supports spi mode ? designed for portable and stationary applications that require high performance and reliable data storage ? voltage range 2.7 v to 3.6 v ? variable clock rate 0-25 mhz (default), 0-50mhz (high-speed) ? up to 25 mb/sec bus transfer rate (using 4 parallel data lines) ? correction of memory-field errors ? built-in write protection features (permanent and temporary) ? application-specific commands ? standard footprint across all capacities 1.3 document scope this document describes the key features and specifications of the sandisk inand as well as the information required to interface it to a host system. chapter 2 describes the physical and mechanical properties of inand, chapter 3 contains the pins and register overview, and chapter 4 gives a general overview of the sd protocol. information about spi protocol can be referenced in section 7 of the sda physical layer specification , version 2.00 . 1.4 inand standard sandisk inand devices are fully compatible with the sda physical layer specification , version 2.00 . this specification is available from the sd card association (sda). sd card association 2400 camino ramon, suite 375 san ramon, ca 94583 usa telephone: +1 (925) 275-6615 fax: +1 (925) 886-4870 e-mail: office@sdcard.org web site: www.sdcard.org
chapter 1 ? introduction revision 1.1 preliminary sandisk inand product manual ? 2007 sandisk corporation 1-3 02/09/07 1.5 functional description the sandisk inand contains a high-level, in telligent subsystem as shown in figure 1-1. this intelligent (microprocessor) subsystem provides many capabilities not found in other types of memory cards. these capabilities include: ? host independence from details of erasing and programming flash memory ? sophisticated system for managing defects (analogous to systems found in magnetic disk drives) ? sophisticated system for error recovery including a powerful ecc ? power management for low power operation 1.6 technology independence the 512-byte sector size of the sandisk inan d is the same as that in an ide magnetic disk drive. to write or read a sector (or multiple sectors), the host software simply issues a read or write command to the card. the command contains the address and number of sectors to write or read. the host software then waits for the command to complete. the host software does not get involved in th e details of how the flash memory is erased, programmed or read. this is extremely import ant because flash devices are expected to get increasingly complex in the fu ture. because inand use an in telligent on-board controller, host system software will not need to be updated as new flash memory evolves. in other words, systems that support inand technology today will be able to access future sandisk devices built with new flash technology without having to update or change host software. 1.7 defect and error management the sandisk inand contains a sophisticated defect and error management system. this system is analogous to the systems found in ma gnetic disk drives and in many cases offers enhancements. if necessary, inand will rewrite data from a defective sector to a good sector. this is completely transparent to the host and does not consume any user data space. the soft error rate specification for inand is much better than the magnetic disk drive specification. in the extremely rare case that a read error does occur, inand has innovative algorithms to recover the data. these defect and error management systems, coupled with the solid state construction, give sandisk inand unparalleled reliability. 1.8 wear leveling wear-leveling is an intrinsic part of the erase pooling functionality of inand. 1.9 automatic sleep mode a unique feature of inand is automatic entrance and exit from sleep mode. upon completion of an operation, cards enter sleep mode to conserve power if no further commands are received in less than 5 millisecon ds (ms). the host does not have to take any action for this to occur. however, in order to achieve the lowest sl eep current, the host needs to shut down its clock to the card. in most systems, cards are in sleep mode except when accessed by the host, thus conserving power.
chapter 1 ? introduction revision 1.1 preliminary sandisk inand product manual ? 2007 sandisk corporation 1-4 02/09/07 when the host is ready to access a card in sleep mode, any command issued to it will cause it to exit sleep, and respond. 1.10 inand ? sd bus mode the following sections provide valuable information on sandisk inand in sd bus mode. sandisk inand devices are fully compliant with the sda physical layer specification , version 2.00 . card specific data (csd) register structures are compliant with csd structure 1.0 and 2.0. this section covers negotiating operating co nditions, card acquisition and identification, card status, memory array partitioning, read/w rite operations, data transfer rate, data protection in flash cards, write protection, copy bit, and csd register. additional practical card detection methods can be found in application notes pertaining to the sda physical layer specification , version 2.00 . figure 1-2 memory array partitioning sandisk inand2 sector 1 sector 2 sector 3 sector n wp group 0 block 0 wp group 1 wp group 2 block 1 block 2 block n
chapter 1 ? introduction revision 1.1 preliminary sandisk inand product manual ? 2007 sandisk corporation 1-5 02/09/07 figure 1-3 data transfer formats table 1-1 mode definitions mode description single block in this mode the host reads or writes one data block in a pre-specified length. the data block transmission is protected with 16-bit crc that is generated by the sending unit and checked by the receiving unit. the block length for read operations is limited by the device sector size (512 bytes) but can be as small as a single byte. misalignment is not allowed. every data block must be contained in a single physical sector. the block length for write operations must be identical to the sector size and the start address aligned to a sector boundary. multiple block this mode is similar to the single block mode, except for the host can read/write multiple data blocks (all have the same lengt h) that are stored or retrieved from contiguous memory addresses starting at the address specified in the command. the operation is terminated with a stop transmission command. misalignment and block length restrictions apply to multip le blocks and are identical to the single block read/write operations. 1.11 spi mode the spi mode is a secondary communication protocol for inand devices. this mode is a subset of the sd protocol, designed to communicate with an spi channel, commonly found in motorola and other vendors? microcontrollers. table 1-1 contains names and descriptions of spi mode functions. more information about spi mode can be found in section 7 or the sda physical layer specification , version 2.00 . multiple block mode memory sectors memory sectors memory sectors memory sectors memory sectors memory sectors memory sectors memory sectors memory sectors memory sectors memory sectors memory sectors memory sectors memory sectors start address (write) start address (read/write) start address (read) write start address stop start read stop single block mode misalignment error
chapter 2 ? product specifications revision 1.1 preliminary sandisk inand product manual ? 2007 sandisk corporation 2-1 02/09/07 2 product specifications 2.1 overview for details about the environmental, reliability and durability specifications, refer to section 8.1 of the sda physical layer specification , version 2.00. 2.2 typical card power requirements table 2-1 inand power requirements (ta=25c@3.0v) vdd (ripple: max, 60mv peak-to-peak) 2.7 v ? 3.6 v value measurement average sleep 250 ua max. read default speed 100 ma max. high-speed 200 ma max. write default speed 100 ma max. high-speed 200 ma max. note: current measurement numbers are average over 1 second. 2.3 operating conditions 2.3.1 operating and storage temperature specifications table 2-2 operating and storage temperatures operating -25 c to 85 c non-operating: after soldered onto pc board -40 c to 85 c temperature non-operating: in tape/reel -10 c to 50 c 2.3.2 moisture sensitivity the moisture sensitivity level for inand is msl = 3.
chapter 2 ? product specifications revision 1.1 preliminary sandisk inand product manual ? 2007 sandisk corporation 2-2 02/09/07 2.4 system performance all performance values for inand in table 2-3 were measured using the following conditions: ? voltage range 2.7 v to 3.6 v ? temperature -25 c to 85 c table 2-3 system performance timing maximum value block read access time 100 ms block write access time 250 ms cmd1 to ready after power-up 1000 ms 2.5 system reliability and maintenance table 2-4 reliability and maintenance specifications mtbf >1,000,000 hours preventative maintenance none data reliability <1 non-recoverable error in 10 14 bits read
chapter 2 ? product specifications revision 1.1 preliminary sandisk inand product manual ? 2007 sandisk corporation 2-3 02/09/07 2.6 physical specifications the sandisk inand is a 169-pin, thin fine-pitc hed ball grid array (bga). see figure 2-1 (169-pin) for physical specifications and dimensions. see figure 2-5 for a top view of the pin definitions. figure 2-1 inand specifications figure 2-2 inand specifications (top view) (a, b)
chapter 2 ? product specifications revision 1.1 preliminary sandisk inand product manual ? 2007 sandisk corporation 2-4 02/09/07 figure 2-3 inand specifications (detail a) figure 2-4 inand specifications (detail b)
chapter 2 ? product specifications revision 1.1 preliminary sandisk inand product manual ? 2007 sandisk corporation 2-5 02/09/07 table 2-5 inand package specifications dimension in millimeters dimension in inches symbol minimum nominal maximum minimum nominal maximum a --- --- 1.20 --- --- 0.047 a1 0.16 0.21 0.26 0.006 0.008 0.010 a2 0.785 0.835 0.885 0.031 0.033 0.035 c 0.17 0.21 0.25 0.007 0.008 0.010 d 11.90 12.00 12.10 0.469 0.472 0.476 e (a) 1 15.90 16.00 16.10 0.626 0.630 0.634 e (b) 2 17.90 18.00 18.10 .7047 .7087 .7126 d1 --- 1.50 --- --- 0.059 --- d2 --- 3.50 --- --- 0.138 --- d3 --- 5.50 --- --- 0.217 --- d4 --- 6.50 --- --- 0.256 --- e1 --- 6.50 --- --- 0.256 --- e2 --- 10.50 --- --- 0.413 --- e3 --- 12.50 --- --- 0.492 --- e4 --- 13.50 --- --- 0.531 --- e --- .50 --- --- 0.020 --- b 0.25 0.30 0.35 0.010 0.012 0.014 aaa 0.10 0.004 bbb 0.10 0.004 ddd 0.08 0.003 eee 0.15 0.006 fff 0.05 0.002 md/me 14/14 14/14 1 these measurements are for the 16 x 12mm package. 2 these measurements are for the 18 x 12mm package.
chapter 2 ? product specifications revision 1.1 preliminary sandisk inand product manual ? 2007 sandisk corporation 2-6 02/09/07 figure 2-5 inand ball array (top view) 2 3 4 5 6 7 8 9 11 12 13 14 1 10 a b c d e f g h j k l m n p
chapter 3 ? inand interface description revision 1.1 preliminary sandisk inand product manual ? 2007 sandisk corporation 3-1 02/09/07 3 inand interface description 3.1 pins and registers table 3-1 contains the sandisk inand functional pin assignment table 3-1 inand pin assignment pin no. name pin no. name pin no. name pin no. name a1 dnu d2 nc j2 nc n5 vss a2 dnu d3 nc j3 nc n6 nc a3 dat0 d4 nc j5 nc n7 nc a4 dat1 d12 dnu j10 vdd_f n8 nc a5 dat2 d13 dnu j12 dnu n9 nc a6 nc d14 dnu j13 dnu n10 nc a7 nc e1 nc j14 dnu n11 nc a8 nc e2 nc k1 nc n12 nc a9 nc e3 nc k2 nc n13 nc a10 nc e5 nc k3 nc n14 dnu a11 nc e6 vdd_f k5 nc p1 dnu a12 nc e7 vss k6 nc p2 dnu a13 dnu e8 nc k7 nc p3 vdd_h a14 dnu e9 nc k8 vss p4 vss b1 dnu e10 nc k9 vdd_f p5 vdd_h b2 dat3 e12 dnu k10 nc p6 vss b3 nc e13 dnu k12 dnu p7 nc b4 nc e14 dnu k13 dnu p8 nc b5 nc f1 nc k14 dnu p9 nc b6 nc f2 nc l1 nc p10 nc b7 nc f3 nc l2 nc p11 nc b8 nc f5 vdd_f l3 nc p12 nc b9 nc f10 nc l12 dnu p13 dnu b10 nc f12 dnu l13 dnu p14 dnu b11 nc f13 dnu l14 dnu
chapter 3 ? inand interface description revision 1.1 preliminary sandisk inand product manual ? 2007 sandisk corporation 3-2 02/09/07 pin no. name pin no. name pin no. name pin no. name b12 nc f14 dnu m1 nc b13 nc g1 nc m2 nc b14 dnu g2 nc m3 nc c1 nc g3 nc m4 vdd_h c2 fcap g5 vss m5 cmd c3 nc g10 nc m6 clk c4 vss g12 dnu m7 nc c5 nc g13 dnu m8 nc c6 vdd_h g14 dnu m9 nc c7 nc h1 nc m10 nc c8 nc h2 nc m11 nc c9 nc h3 nc m12 dnu c10 nc h5 nc m13 dnu c11 nc h10 vss m14 dnu c12 dnu h12 dnu n1 dnu c13 dnu h13 dnu n2 vss c14 dnu h14 dnu n3 nc d1 nc j1 nc n4 vdd_h sandisk inand contains a set of information registers. register descriptions and sda references are provided in section 5.0 of the sda physical layer specification , version 2.00 . table 3-2 inand register overview register abbreviation width (in bits) register name cid 128 card identification number rca 16 relative card address csd 128 card specific data scr 64 sd configuration ocr 32 operation conditions ssr 512 sd status csr 32 card status; information about the card status.
chapter 3 ? inand interface description revision 1.1 preliminary sandisk inand product manual ? 2007 sandisk corporation 3-3 02/09/07 3.2 bus topologies sandisk inand products support two communication protocols: sd and spi. for more details, refer to section 3.5 of the sda physical layer specification , version 2.00 . section 6 of the specification contains a bus circuitry diagram for reference . 3.2.1 sd bus for more details, refer to section 3.5.1 of the sda physical layer specification, version 2.00. 3.2.2 spi bus for more details, refer to section 3.5.2 of the sda physical layer specification, version 2.00. 3.3 electrical interface the power scheme of sandisk inand is handl ed locally in each card and in the bus master. refer to section 6.4 of the sda physical layer specification , version 2.00 . 3.3.1 power up refer to section 6.4.1 of the sda physical layer specification, version 2.00 . 3.3.2 bus operating conditions spi mode bus operating conditions are identical to sd bus mode operating conditions. for details, see section 6.6 of the sda physical layer specification , version 2.00 . 3.3.3 bus timing (default) see section 6.7 of the sda physical layer specification, version 2.00. 3.3.4 bus timing (high-speed mode) see section 6.8 of the sda physical layer specification, version 2.00 . 3.4 inand registers there is a set of eight registers within the inand interface. for specific information about each register, refer to section 5 of the sda physical layer specification, version 2.00 . 3.4.1 operating conditions register the operation conditions register (ocr) stores the vdd voltage profile for inand. refer to section 5.1 of the sda physical layer specification , version 2.00 . 3.4.2 card identification register the card identification (cid) register is 16 bytes long and contains the unique card identification number. it is programmed during manufacturing and cannot be changed by inand hosts. see table 3-4.
chapter 3 ? inand interface description revision 1.1 preliminary sandisk inand product manual ? 2007 sandisk corporation 3-4 02/09/07 table 3-4 cid register definitions name type width cid value comments manufacturer id (mid) binary 8 0x03 manufacturer ids are controlled and assigned by the sd-3c, llc oem/application id (oid) ascii 16 sd ascii code 0x53, 0x44 identifies the card oem and/or the card contents. the oid is controlled and assigned by the sd-3c, llc st08g st04g st02g st01g product name (pnm) ascii 40 st512 five ascii characters long product revision (prv) bcd 8 product revision xx see section 5.2 in the sda physical layer specification , version 2.00 serial number (psn) binary 32 product serial number 32-bit unsigned integer reserved --- 4 --- --- manufacture date code (mdt) bcd 12 manufacture date (for ex. april 2001= 0x014) manufacturing date?yym (offset from 2000) crc7 checksum ( crc ) binary 7 crc7* calculated not used, always --- 1 --- --- note: sd-3c, llc is a limited liability company established by matsushita electric industrial co. ltd., sandisk corporation and toshiba corporation. *the crc checksum is computed by using the following formula: crc calculation: g(x) = x 7 +x 3 +1 m(x)=(mid-msb)*x 119 +?+(cin-lsb)*x 0 crc[6?0]=remainder[(m(x)*x 7 )/g(x)]
chapter 3 ? inand interface description revision 1.1 preliminary sandisk inand product manual ? 2007 sandisk corporation 3-5 02/09/07 3.4.3 card specific data register the card specific data (csd) register configuration information is required to access inand data. the csd defines the data format, error correction type, maximum data access time, etc. the field structures of the cs d register vary depending on the physical specifications and card capacity. the csd_structure field in the csd register indicates which structure version is used. ta ble 3-5 shows the version number as it relates to the csd structure. refer to section 5.3.1 of the sda physical layer specification, version 2.00 for more information. table 3-5 csd register structures csd_structure csd structure version valid for sd memory card physical specification version / card capacity version 1.01 to 1.10 0 csd version 1.0 version 2.00 / standard capacity 1 csd version 2.0 version 2.00 / high capacity 2-3 reserved --- table 3-6 provides an overview of the csd re gister. more field-sp ecific information can be found in section 5.3.2, table 5-4 of the sda physical layer specification, version 2.00 . table 3-6 csd register (csd version 1.0) field csd value description csd_ structure 1.0 csd structure --- --- reserved taac 1.5 msec data read access time-1 nsac 0 data read access time-2 in clk cycles (nsac*100) default 25mhz trans_ speed high-speed 50mhz max. data transfer rate ccc all (inc. wp, lock/unlock) card command classes read_bl_ len 2g up to 1g max. read data block length read_bl_ partial yes partial blocks for read allowed write_blk_ misalign no write block misalignment read_blk_ misalign no read block misalignment dsr_imp no dsr implemented --- --- reserved c_size 2 gb 1 gb 512 mb device size vdd_r_ curr_min according to card performance max. read current @vdd min. vdd_r_ curr_max according to card max. read current @vdd max.
chapter 3 ? inand interface description revision 1.1 preliminary sandisk inand product manual ? 2007 sandisk corporation 3-6 02/09/07 field csd value description performance vdd_w_ curr_min according to card performance max. write current @vdd min. vdd_w_ curr_max according to card performance max. write current @vdd max. c_size_ mult 2g=2048 1g=1024 512=512 device size multiplier erase_blk_en yes erase single block enable sector_ size 32 blocks erase sector size wp_grp_ size 128 sectors write protect group size wp_grp_ enable yes write protect group enable reserved --- reserved for mmc compatibility r2w_ factor x16 write speed factor write_bl_ len 2g up to 1g max. write data block length write_bl partial no partial blocks for write allowed --- --- reserved file_ format_ grp 0 file format group copy has been copied copy flag (otp) perm_ write_ protect not protected permanent write protection tmp_write_protect not protected temporary write protection file_ format hd w/partition file format reserved --- reserved crc crc7 crc --- --- not used, always ?1?
chapter 3 ? inand interface description revision 1.1 preliminary sandisk inand product manual ? 2007 sandisk corporation 3-7 02/09/07 refer to section 5.3.3, table 5-16 of the sda physical layer specification, version 2.00 for more detailed information. table 3-7 csd register (csd version 2.0) field csd value description csd_ structure 2.0 csd structure --- --- reserved taac 1.5 ms data read access time-1 nsac 0 data read access time-2 in clk cycles (nsac*100) default 25mhz trans_ speed high-speed 50mhz max. data transfer rate ccc 010110110101b card command classes read_bl_ len --- max. read data block length read_bl_ partial yes partial blocks for read allowed write_blk_ misalign no write block misalignment read_blk_ misalign no read block misalignment dsr_imp no dsr implemented --- 0 reserved 8 gb c_size 4 gb device size --- 0 reserved erase_blk_en 1 erase single block enable sector_ size 32 blocks erase sector size wp_grp_ size 128 sectors write protect group size wp_grp_ enable yes write protect group enable reserved --- reserved for mmc compatibility r2w_ factor x16 write speed factor write_bl_ len --- max. write data block length write_bl partial no partial blocks for write allowed --- --- reserved file_ format_ grp 0 file format group copy has been copied copy flag (otp) perm_ write_ protect not protected permanent write protection tmp_write_protect no protected temporary write protection file_ format hd w/partition file format reserved --- reserved
chapter 3 ? inand interface description revision 1.1 preliminary sandisk inand product manual ? 2007 sandisk corporation 3-8 02/09/07 field csd value description crc crc7 crc --- --- not used, always ?1? 3.4.4 card status register the card status register (csr) transmits the card?s status information (which may be stored in a local status register) to the host. the csr is defined in section 4.10.1 in the sda physical layer specification, version 2.00 . 3.4.5 sd status register the sd status register (ssr) contains status bits that ar e related to inand proprietary features and may be used for future applications. the sd status structure is described in section 4.10.2 in the sda physical layer specification, version 2.00 . 3.4.6 relative card address register the 16-bit relative card address (rca) register carries the card address published by the card during the card identification. refer to section 5.4 in the sda physical layer specification, version 2.00 for more information. 3.4.7 sd card configuration register the sd card configuration register (scr) is in addition to the csd register. the scr provides information about sp ecial features in sandisk in and. for more information, refer to section 5.6 in the sda physical layer specification, version 2.00 . 3.4.8 sd card registers in spi mode all registers are accessible in spi mode. their fo rmat is identical to the format in the sd bus mode, however a few fields are irrelevant in spi mode. in spi mode, the card status register has a different, shorter, format as well. refer to section 7.4 in the sda physical layer specification, version 2.00 . for more details. 3.5 data interchange format and card sizes in general, a file system provides structure for inand data. the sd card file system specification, published by the sd association, describes the file format system implemented in the sandisk inand.
chapter 3 ? inand interface description revision 1.1 preliminary sandisk inand product manual ? 2007 sandisk corporation 3-9 02/09/07 table 3-8 user area dos image parameters capacity* total lbas number of partition system area sectors total partition sectors user data sectors user data bytes 8 gb 16,055,296 8192 16,047,104 16,038,912 3,073,376,256 4 gb 8,026,112 8192 8,017,920 8,009,728 4,100,980,736 2 gb 4,013,056 523 4,011,595 4,011,072 2,053,668,864 1 gb 2,006,528 523 2,005,675 2,005,152 1,026,637,824 512 mb 1,003,264 279 1,002,727 1,002,448 513,253,376 * 1 megabyte (mb) = 1 million bytes; 1 gi gabyte (gb) = 1 billion bytes. some of the listed capacity is used for formatting and other functions, and thus is not available for data storage.
chapter 4 ? inand protocol description revision 1.1 preliminary sandisk inand product manual ? 2007 sandisk corporation 4-1 02/09/07 4 inand protocol description 4.1 general description inand protocol information is contained in this chapter; information includes bus protocol, card identification, and a functional description. 4.2 sd bus protocol communication over the sd bus is based on command and data-bit streams initiated by a start bit and terminated by a stop bit. see section 3.6.1 of the sda physical layer specification, version 2.00 for details. 4.3 functional description the host controls all communication between itself and inand. to demonstrate how this communication works, this section provides a general overview of the card identification and data transfer modes; commands; card dependencies; various card operation modes and restrictions for controlling the clock signal. all inand commands, together with corresponding responses, state transitions, erro r conditions, and timings are also provided. for detailed information, refer to section 4 of the sda physical layer specification , version 2.00 . 4.3.1 card identification mode in card identification mode the host resets all cards, validates operation voltage range, identifies and requests cards to publish a rela tive card address. for more information see section 4.2 in the sda physical layer specification , version 2.00 . 4.3.2 data transfer mode in data transfer mode, the host may operate inand in the f pp frequency range. this section contains information about data read and write, erase, write protect management, card lock/unlock operations, application-specific commands, the switch function command, high-speed mode, the command system, the send interface condition command (cmd8). cmd8 is part of identification mode and command functional differences in high capacity inand. for more detailed information, refer to section 4.3 of the sda physical layer specification , version 2.00 . 4.3.3 clock control the host can use the bus clock signal in inan d to switch them to energy saving mode or to control data flow on the bus. see section 4.4 of the sda physical layer specification , version 2.00 .
chapter 4 ? inand protocol description revision 1.1 preliminary sandisk inand product manual ? 2007 sandisk corporation 4-2 02/09/07 4.3.4 cyclic redundancy codes the cyclic redundancy check (crc) protects against transmission errors that may occur on the inand bus. detailed information and examples for crc7 and crc16 are provided in section 4.5 of the sda physical layer specification , version 2.00 . 4.3.5 error conditions see section 4.6 of the sda physical layer specification , version 2.00 . 4.3.6 commands see section 4.7 of the sda physical layer specification , version 2.00 for detailed information about inand commands. 4.3.7 card state transition the state transition is dependent on the received command. the transition is defined in section 4.8 of the sda physical layer specification , version 2.00 along with responses sent on the command line. 4.3.8 timing diagrams and values see section 4.12 of the sda physical layer specification , version 2.00 . 4.3.9 speed class specification the speed class specification cl assifies card performance by speed class number and offers the method to calculate performance. for more information, refer to section 4.13 of the sda physical layer specification , version 2.00 . 4.3.10 erase timeout calculation see section 4.14 of the sda physical layer specification , version 2.00 .
appendix a ?power delivery/capacitor specifications revision 1.1 preliminary sandisk inand product manual ? 2007 sandisk corporation a-1 02/09/07 appendix a power delivery a nd capacitor specifications a.1 sandisk inand power domains sandisk inand has three power domains assigned to vdd_h, vdd_f, and fcap as shown in table 1. table 1. power domains pin power domain comments supported voltage ranges: high voltage region: 3.3v (nominal) vdd_h host interface low voltage region: 1.8v (nominal) supported voltage range: vdd_f memory high voltage region: 3.3v (nominal) fcap internal fcap is the internal regulator connection to an external decoupling capacitor. a.2 capacitor connection guidelines a.2.1 fcap connections the fcap (c2) ball must only be connected to an external capacitor th at is connected to vss. this signal may not be left floating. the capacitor?s specifications and its placement instructions are detailed below. the capacitor is part of an internal voltage regulator that provides power to the controller. caution: failure to follow the guidelines below or connecting the fcap ball to any external signal or power supply ma y cause the device to malfunction. the trace requirements from the fcap (c2) ball to the capacitor are as follows: ? resistance: <2 ohm ? inductance: <5 nh the capacitor requirements are as follows: ? capacitance: >=2.2 uf ? voltage rating: >=6.3 v ? dielectric: x7r or x5r
appendix a ?power delivery/capacitor specifications revision 1.1 preliminary sandisk inand product manual ? 2007 sandisk corporation a-2 02/09/07 a.2.2 vdd_h and vdd_f connections the inand has two power domains labeled: vdd_h and vdd_f. currently both power domains can be connected to the same 3.3v (nom) power supply. however, in order to provide maximum flexibility and support low power operation in future inand devices, the pcb should be designed as follows: ? all vdd_f balls should be connected to a 3.3v supply ? all vdd_h balls should have the option of being connected either to a 3.3v or 1.8v supply sandisk recommends providing separate bypass capacitors for each power domain as shown in figure 1. note : signal routing in the diagram is for illustration purposes only and the final routing depends on your pcb layout. also, for clarity, the diagram does not show the vss connection. all balls marked vss should be connected to a ground (gnd) plane. figure 1. recommended power domain connections j10 vdd_ f k9 vdd_ f c6 vdd_ h e6 vdd_ f p5 vdd_ h m4 vdd _h n4 vdd_ h 14 13 12 11 10 9 8 7 6 5 4 3 2 1 abcdefghjklmnp p3 vdd_h f5 vdd_f c_1 c_2 c_3 c_4 c_5 vss vss vss vss vss c_1=c_3>=2.2uf c_2=c_4<=100nf close to ball f5 close to ball p3 capacitor c_5: capacitance >= 2.2uf voltage >= 6.3v dielectric: x7r or x5r trace requirements (c_5): resistance < 2 ohm inductance < 5nh c2 fcap top view vdd_h power supply vdd_f = 3.3v (nom)
appendix b ?ordering information revision 1.1 preliminary sandisk inand product manual ? 2007 sandisk corporation b-1 02/09/07 appendix b ordering information b.1 inand (jc64 package) to order sandisk products directly from sandisk, call (408) 801-1000. part number block size 1 12 mm x 16 mm x 1.2 mm package sdin2c1-512m 512 mb sdin2c2-1g 1 gb SDIN2C2-2G 2 gb 12 mm x 18 mm x 1.2 mm package sdin2b2-2g 2 gb sdin2b2-4g 4 gb sdin2b2-8g 8 gb note: if parts will be shipped by tape/reel, add ?t? to the end of the part number. for example, sdin2b2-8g would become sdin2b2-8g-t. 1 1 megabyte (mb) = 1 million bytes; 1 gi gabyte (gb) = 1 billion bytes. some of the listed capacity is used for formatting and other functi ons, and thus is not available for data storage.
appendix c ?disclaimer of liability revision 1.1 preliminary sandisk inand product manual ? 2007 sandisk corporation c-1 02/09/07 appendix c disclaimer of liability c.1 sandisk corporation policy sandisk corporation general policy does not recommend the use of its products in life support applications wherein a failure or malfunction of the product may directly threaten life or injury. accordingly, in any use of products in life support systems or other applications where failure could cause damage, injury or loss of life, the products should only be incorporated in systems designed with appropriate redundancy, fault tolerant or back-up features. sandisk shall not be liable for any loss, injury or damage caused by use of the products in any of the following applications: ? special applications such as military relate d equipment, nuclear reactor control, and aerospace ? control devices for automotive vehicles , train, ship and traffic equipment ? safety system for disaster prevention and crime prevention ? medical-related equipment including medical measurement device

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